1. Field of the Invention
The present invention relates to a slope etching process, and particularly to a slope etching process which provides a smooth slope for the pattern formed in manufacturing semi-conductor elements, thereby improving the step coverage.
2. Description of the Prior Art
In order to form a desired pattern in manufacturing semiconductor elements, photo processing and etching should be generally carried out. The etching is mainly classified into a dry etching process and a wet etching process, a suitable one of which is used depending on the existing conditions.
Recently, RIE (Reactive Ion Etching) method which is generally classified as the dry etching method is gradually being widely used in view of its convenience in processing over the wet etching method.
In forming a pattern, the conventional RIE method enables only anisotropic etching, so that the pattern of etched layer is formed such that its corner angle becomes about 90.degree..
The conventional pattern forming process utilizing the above-mentioned RIE method will now be described, in conjunction with FIGS. 1A to 1D.
First, a layer 2 for forming a predetermined pattern is deposited on a substrate 1, as shown in FIG. 1A. The layer 2 will be subsequently etched to form a pattern. On the layer 2, a photoresist 3 is coated and then radiated with ultra violet radiation under the condition that a photomask 4 is aligned on the photoresist 3 to be in contact therewith, in order to form a pattern layer 3a as shown in FIG. 1B. Thereafter, the layer 2 for forming a desired pattern is subjected to an etch utilizing the RIE method which is an anisotropic dry etch method. After the photoresist pattern layer 3a is removed from the etched pattern forming layer 2, a pattern layer 2a having corner angles of 90.degree. is formed, as shown in FIG. 1D. However, the pattern forming utilizing the conventional RIE method has a disadvantage that when a primary upper deposition layer 5 is coated on the pattern layer 2a etched according to the RIE method, the step coverage, that is the coverage of the deposition layer 5 over steps (the "K" portion in FIG. 2) formed at respective corners of about 90.degree. of the pattern layer 2a, becomes poor, after the process integration. Consequently, the pattern layer 2a formed by the RIE method and a second upper deposition layer 6 formed on the primary upper deposition layer 5 is subject to a short failure, thereby causing the productivity of semi-conductor elements to be reduced.
Also, the pattern forming process utilizing the conventional wet etching method will now be described, in conjunction with FIGS. 3A to 3D.
First, a pattern forming layer 8 to be etched is deposited on a substrate 7, as shown in FIG. 3A. On the layer 8, a photoresist 9 is coated. Then, the photoresist 9 is exposed to ultra violet radiation by using a photomask 10 printed with a predetermined pattern and developed to form a photoresist pattern layer 9a as shown in FIG. 3B. Thereafter, the wet etching is carried out as shown in FIG. 3C. At this time, the pattern forming layer 8 is isotropically etched. This is because the velocity V.sub.S of the etching which proceeds on the interface between the photoresist 10 and the pattern forming layer 8 and in parallel to said interface is substantially identical to the velocity V.sub.D of the etching which proceeds vertically to the surface of the element material (V.sub.S =V.sub.D). As a result, a pattern layer 8a is formed such that its lateral edges form an angle of 45.degree. to the surface of substrate 7. As the photoresist pattern layer 9a is removed, a desired pattern layer 8a is formed, as shown in FIG. 3D. However, the pattern forming utilizing the conventional wet etching process also has a disadvantage that when a primary upper deposition layer 11 is coated on the pattern layer 8a etched according to the RIE method, its step coverage over respective 45.degree. lateral edges of the pattern layer 8a becomes poor. Consequently, the pattern layer 8a and a second upper deposition layer 12 formed on the primary upper deposition layer 11 are subject to a short failure (at the portion "L" in FIG. 4). In particular, when the pattern layer 8a and the second upper deposition layer 12 form metal electrodes and the primary upper deposition layer forms an insulation layer, the pattern layer 8a and the second upper deposition layer 12 may be subject to a break down at the portion "L", thereby causing the productivity of semiconductor elements to be reduced.